This invention relates to a semiconductor memory device and particularly to a semiconductor memory device capable of a rapid read-out of stored data.
Thanks to recent developments of art in semiconductors, many types of semiconductor memory devices have been proposed for the purpose of data storing. Memory devices capable of a rapid read-out of stored data have been demanded to expedite the overall speed of data processing. Upon detection of stored data in such a memory device, column lines in a memory array of memory cells consisting of a matrix array of MOS transistors (hereinafter called MOS FET's) are charged by means of a pull-up transistor, and when one of the column lines is coupled with a selected one of the memory cells, a charge on the column line either is or is not discharged in response to a binary content in the cell. A voltage sensor connected with the column lines detects the charge of the column line to generate an output signal indicative of a binary content in the cell. It is thus apparent that periods of time for charging the column lines and discharging the charge therefrom must be shortened for providing a rapid read-out of data in a semiconductor memory device. It is preferred that the pull-up transistor have a sufficiently small conduction resistance to permit a rapid action of charging the column lines. A pull-up transistor which has a small conduction resistance, however, forms a resistance to the discharging action of the charge on the column lines, thus resulting in a lengthened time of discharging action. It is therefore desired that a pull-up transistor have a low resistance upon the charging action and a high resistance upon the discharging action of a semiconductor memory device; but, it is not feasible to so change a resistance value of the pull-up transistor, so that a period of time for only either one of the charging or the discharging actions has been proposed in the prior art to be shortened at the cost of another.